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Xilinx:Pipelined Divider
类型:软IP
简短描述:Pipelined Divider
详细描述:The Pipelined Divider IP core divides a variable dividend by a variable divisor to give a quotient with an integer or fractional remainder. Input data throughput can be increased by selecting the pipelining option for the module. Both signed (two's complement format) and unsigned data are supported. Dividend values can range from 1 to 24 bits, divisor values can range from 3 to 24 bits, and fractional remainder values may range from 3 to 24 bits.
工艺:0.25um
代工厂:
应用:
特色:

    Xilinx:Pipelined Divider
    Xilinx:Twos Complementer
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