The ZSP600 Core is a highly parallel, high performance Quad MAC / Six ALU processor designed to meet the high demands of today's most intensive digital signal processing applications. ZSP600 provides performance level demanded by 3G wireless base station processing and voice network infrastructure applications, while maintaining a far easier programming model than other high-end DSPs. The ZSP600 core's combination of code density and processing performance make it a great choice for implementing cost-reduced systems currently based on costly discrete DSP and memory devices.

VeriSilicon ZSP DSP cores are fully synthesizable and completely technology independent. The Cores have been proven in ASICs and standard products alike. The ZSP architectures have been optimized for optimal code density, energy efficiency, compiler performance and system integration.
 

6 instructions per cycle, Quad MAC / Six ALU DSP core 
Runs up to 300 MHz in 0.13um
Automatic and programmer controlled power  management 
Customizable instruction set using Z.turbo port 
Extensive 32-bit and 40-bit support 
Dual, independent 64-bit load/store ports 
16/32-bit instruction set 
24-bit address space for both instruction and data memory 
Orthogonal, load-store instruction set 
Hardware controlled pipeline protection 
Synthesizable, single phase clocked design 
Code compatible with all other ZSP cores 
Embedded trace and profiling capability 
Available with full AMBA (AHB) support