A semiconductor IP core that implements a video display converter producing standard video data and control signals ready for further processing by an NTSC or PAL broadcast signal encoder. The video data the core produces conforms to the ITU-R BT.601/BT.656 recommendation (formerly CCIR-601 and CCIR-656).

The video display core accepts three different input formats and produces standard 4:2:2 YCbCr pixel data. It also generates all the horizontal and vertical timing periods required for broadcast: horizontal and vertical front porch, back porch, and sync intervals. The core’s output signals are compatible with the popular Analog Devices’ ADV7174/79 or similar NTSC/PAL video encoder chip.

Ready for easy integration with AMBA-based microprocessor systems, the TVOUT-CTRL includes a wrapper that efficiently interfaces the core DMA, FIFO, and control logic functions with the AMBA High-Speed Bus (AHB).

The core is designed for efficient implementation, good performance, and straightforward testing in an ASIC or FPGA SoC design. Typical ASIC results (0.18 μm) show it to require from 14,300 gates for 100 MHz speed to 15,200 gates for 200 MHz.