This is a Power-On-Reset circuit that generates a reset pulse when power supply is on. After the power AVDD18 reaches a specific level, VTR, it will output a logic reset signal with pulse width of tPOR. During this interval, all the logic elements can be initialized to known states. When the power drops to another level VTF or the PD goes from high to low, a reset pulse is also generated. The additional input RSTI can force the POR to output a reset signal, providing a soft reset function. If the power supply乫s rise time is longer than 400us, the reset pulse will not occur after the power supply is stable.

Process: SMIC0.18 Low Leakage 1P4M logic process  
Operating voltage range: AVDD18: 0~2V AVDD33: 0~3.6V  
Operating temperature range: -40~125 c  
No external components required (VREF and IBN are reference voltage and current each from another on-chip analog block)  
Active current: Idd<15uA (if bias current <1.5uA)  
Power-on reset pulse width: tPOR: 80~200us